Thin polished plates such as silicon wafers and the like are a very important part of modern technology. A wafer, for instance, may refer to a thin slice of semiconductor material used in the fabrication of integrated circuits and other devices. Other examples of thin polished plates may include magnetic disc substrates, gauge blocks and the like. While the technique described here refers mainly to wafers, it is to be understood that the technique also is applicable to other types of polished plates as well. The term wafer and the term thin polished plate may be used interchangeably in the present disclosure.
Wafers are available in a variety of sizes. They may also be patterned or presented as bare wafers. Interferometer wafer metrology systems, such as WaferSight metrology system from KLA-Tencor, may scan both the front and back surfaces of a wafer at the same time. By combining wafer shape, edge roll-off, thickness or flatness, and topography measurements in a single scan, such wafer metrology tools may provide complete data sets that are necessary for topography and wafer geometry monitoring in wafer manufacturing.
It is noted, however, that most existing interferometer wafer metrology systems reconstruct the wafer surface by calculating the wrapped surface phase maps from a sequence of measured interferometry image frames and then unwrapping these phase maps for the wafer surface height maps. It is noted that the general two dimensional phase unwrapping for wafer surface height maps may introduce errors and failures have been observed when attempting to reconstruct wafer surface maps of patterned wafers. More specifically, phase signals of a patterned wafer surface obtained using a wafer metrology tool typically contain sharp phase transitions induced by the wafer surface pattern structures. These sharp phase transitions often lead to phase unwrapping errors, which in turn may cause severe artifacts on a reconstructed wafer surface map.
Phase unwrapping methods based on global gradient matching optimization, such as minimum norm phase unwrapping or the like, may be able to provide more robust and accurate phase unwrapping results for patterned wafers. However, such phase unwrapping methods require gradient matching of the acquired wafer surface phase and the reconstructed wafer surface, and also require the phase aliasing errors to be kept small. When used directly on the phase maps obtained from measurements of large shape wafers, gradient matching optimization based phase unwrapping methods will generate large shape artifacts. Severe surface errors have been observed in the wafer areas with large shape slopes.